Receiver nonlinearity estimation and cancellation

ABSTRACT

Systems and methods are provided for receiver nonlinearity estimation and cancellation. Narrowband (NB) estimation may be performed in a receiver during handling of received radio frequency (RF) signals. The narrowband (NB) may include generating estimation channelization information relating to received RF signals; generating reference nonlinearity information relating to one or more other signals, which may cause or contribute to nonlinearity that affects the processing of the received RF signals; and generating, based on the estimation channelization information relating to the received RF signals and the reference nonlinearity information relating to the other signals, control data for configuring nonlinearity cancellation functions. The received RF signals may be channelized, and the estimation channelization information may be generated based on the channelization of the received RF signals. The other signals may be channelized, and the reference nonlinearity information may be generated based on the channelization of the other signals.

CLAIM OF PRIORITY

This patent application is a continuation of U.S. patent applicationSer. No. 16/229,789, filed on Dec. 21, 2018, which is a continuation ofU.S. patent application Ser. No. 15/180,754, filed on Jun. 13, 2016,which makes reference to, claims priority to and claims benefit fromU.S. Provisional Patent Application Ser. No. 62/174,932, filed on Jun.12, 2015. Each of the above identified applications is herebyincorporated herein by reference in its entirety.

TECHNICAL FIELD

Aspects of the present disclosure relate to signal processing. Morespecifically, various implementations of the present disclosure relateto receiver nonlinearity estimation and cancellation.

BACKGROUND

Conventional approaches for handling nonlinearity, particularly at thereceiver-side during communications, may be costly, cumbersome, orinefficient—e.g., they may be complex and/or time consuming, requireconsiderable power, and/or may introduce errors or distortion. Furtherlimitations and disadvantages of conventional and traditional approacheswill become apparent to one of skill in the art, through comparison ofsuch systems with some aspects of the present disclosure as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY

System and methods are provided for receiver nonlinearity estimation andcancellation, substantially as shown in and/or described in connectionwith at least one of the figures, as set forth more completely in theclaims.

These and other advantages, aspects and novel features of the presentdisclosure, as well as details of an illustrated embodiment thereof,will be more fully understood from the following description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example communication arrangement in whichnonlinearity may occur at the receiver-side.

FIG. 2 illustrates an example analog front-end (AFE) in whichnonlinearity may occur during reception operations.

FIGS. 3A and 3B illustrate example impacts of intermodulation (IM) andharmonic distortion (HD) during reception operations.

FIG. 4 illustrates example architecture for nonlinearity correction inreceiver analog front-ends, using narrowband (NB) nonlinearityestimation and wideband (WB) nonlinearity correction.

FIG. 5 illustrates example architecture for narrowband (NB) nonlinearityestimation and wideband (WB) nonlinearity correction.

FIG. 6 illustrates example narrowband (NB) reference generator andcoefficient estimator used for narrowband (NB) nonlinearity estimation.

FIG. 7 illustrates example anti-aliasing filtering (AAF) compensationcircuit for use in nonlinearity correction in receiver analogfront-ends.

FIG. 8 illustrates example nonlinearity cancellation circuit for use innonlinearity correction in receiver analog front-ends.

FIG. 9 illustrates a flowchart of an example process for nonlinearitydetection and correction during communications.

DETAILED DESCRIPTION

As utilized herein the terms “circuits” and “circuitry” refer tophysical electronic components (e.g., hardware), and any software and/orfirmware (“code”) that may configure the hardware, be executed by thehardware, and or otherwise be associated with the hardware. As usedherein, for example, a particular processor and memory (e.g., a volatileor non-volatile memory device, a general computer-readable medium, etc.)may comprise a first “circuit” when executing a first one or more linesof code and may comprise a second “circuit” when executing a second oneor more lines of code. Additionally, a circuit may comprise analogand/or digital circuitry. Such circuitry may, for example, operate onanalog and/or digital signals. It should be understood that a circuitmay be in a single device or chip, on a single motherboard, in a singlechassis, in a plurality of enclosures at a single geographical location,in a plurality of enclosures distributed over a plurality ofgeographical locations, etc. Similarly, the term “module” may, forexample, refer to a physical electronic components (e.g., hardware) andany software and/or firmware (“code”) that may configure the hardware,be executed by the hardware, and or otherwise be associated with thehardware.

As utilized herein, circuitry or module is “operable” to perform afunction whenever the circuitry or module comprises the necessaryhardware and code (if any is necessary) to perform the function,regardless of whether performance of the function is disabled or notenabled (e.g., by a user-configurable setting, factory trim, etc.).

As utilized herein, “and/or” means any one or more of the items in thelist joined by “and/or”. As an example, “x and/or y” means any elementof the three-element set {(x), (y), (x, y)}. In other words, “x and/ory” means “one or both of x and y.” As another example, “x, y, and/or z”means any element of the seven-element set {(x), (y), (z), (x, y), (x,z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one ormore of x, y, and z.” As utilized herein, the term “exemplary” meansserving as a non-limiting example, instance, or illustration. Asutilized herein, the terms “for example” and “e.g.” set off lists of oneor more non-limiting examples, instances, or illustrations.

FIG. 1 illustrates an example communication arrangement in whichnonlinearity may occur at the receiver-side. Shown in FIG. 1 is acommunication arrangement 100, comprising communication devices 110 ₁and 110 ₂, which may communicate via a connection/link 111.

Each of the communication devices 110 ₁ and 110 ₂ may comprise suitablecircuitry for communication over wired and/or wireless connections. Inthis regard, the communication devices 100 may support a plurality ofwired and/or wireless interfaces and/or protocols, and may be operableto perform necessary processing operations to facilitate transmissionand/or reception of signals (e.g., RF signals) over supported wiredand/or wireless interfaces.

Examples of communication devices may include cellular and smart phonesor similar handheld devices, tablets, personal computers, laptops ornotebook computers, servers, personal media players, personal digitalassistants, set top boxes, satellite receivers, wireless access points,cellular base stations, etc. The disclosure is not limited, however, toparticular type of communication devices, and may apply to anyelectronic platform that may be operable to communicate (transmit and/orreceive) signals.

Examples of wireless standards, protocols, and/or interfaces which maybe supported and/or used by the communication devices 110 ₁ and 110 ₂for communication therebetween may comprise wireless personal areanetwork (WPAN) protocols (e.g., as Bluetooth (IEEE 802.15) and ZigBee),near field communication (NFC) standards, wireless local area network(WLAN) protocols (e.g., such as WiFi (IEEE 802.11) standards), cellularstandards (including 2G/2G+, such as GSM/GPRS/EDGE, IS-95 or cdmaOne,etc., and 3G/3G+, such as CDMA2000, UMTS, and HSPA, etc.), 4G standards(e.g., WiMAX (IEEE 802.16) and LTE), Ultra-Wideband (UWB), ExtremelyHigh Frequency (EHF, such as 60 GHz) Digital TV Standards (e.g.,DVB-T/DVB-H, and ISDB-T), etc.

Examples of wireless standards, protocols, and/or interfaces which maybe supported and/or used by the communication devices 110 ₁ and 110 ₂for communication therebetween may comprise Ethernet (IEEE 802.3),Digital Subscriber Line (DSL), Integrated Services Digital Network(ISDN), Fiber Distributed Data Interface (FDDI), cable television and/orinternet access standards (e.g., ATSC, DVB-C, DOCSIS, etc.), in-homedistribution standards such as Multimedia over Coax Alliance (MoCA),Universal Serial Bus (USB) based standards/protocols/interfaces, etc.

In operation, the communication devices 110 ₁ and 110 ₂ may communicateover the connection/link 111. The connection/link 111 may beunidirectional (e.g., allow for communications in only one direction,such as from the communication device 110 ₁ to the communication device110 ₂), or may be bidirectional (e.g., allowing for communications inboth directions—that is from the communication device 110 ₁ to thecommunication device 110 ₂, and from the communication device 110 ₂ tothe communication device 110 ₁) In this regard, the connection/link 111may be configured to allow for concurrent bidirectional communicationsbetween the two devices (e.g., using time division duplex (TDD) and/orfrequency division duplex (FDD) simultaneous transmit and receive(STR)).

Communications over the connection/link 111 may comprise transmissionand reception of signals (e.g., RF signals), which may be utilized tocarry data communicated between the communication devices 110 ₁ and 110₂. The signals communicated over the connection/link 111 may be setup,configured, and/or utilized in accordance with corresponding wiredand/or wireless interfaces, protocols, and/or standards. Thecommunication devices 110 ₁ and 110 ₂ may comprise suitable componentsconfigured to perform various functions or operations to facilitate thetransmission and reception of signals, particularly RF signals. Asimplified RF transmission and reception model is illustrated in FIG. 1.

At the transmitter-side 120, a transmission (Tx) processing path 130 maybe used to generate intermediate frequency (IF) signals. The Txprocessing path 130 may comprise suitable circuitry for generating theIF signals, such as based on digital input (data) that is intended to becarried and/or embedded in the communicated signals. The Tx processingpath 130 may comprise, for example, a modulation circuit 132, adigital-to-analog converter (DAC) circuit 134, a mixer circuit 136, anda power amplifier circuit 138. The IF signals may then be sent to a RFtransmitter 140, which may comprise suitable circuitry for generatingand transmitting radio frequency (RF) signals, such as based on IFsignals provided thereto. The RF signals are then communicated over a RFchannel 150.

At the receiver-side 160, the RF signals may be received from thechannel 150 via a RF receiver 170, which may comprise suitable circuitryfor receiving radio frequency (RF) signals, and processing them togenerate corresponding intermediate frequency (IF) signals. The IFsignals are then sent to a reception (Rx) processing path 180, which maycomprise suitable circuitry for processing IF signals, such as toextract data carried and/or embedded therein (e.g., the digital dataembedded into the RF signals at the transmitter-side). The Rx processingpath 180 may comprise, for example, low-noise amplifier (LNA) circuit182, a mixer circuit 184, digital-to-analog converter (DAC) circuit 186,and a demodulator circuit 132.

In some instances, performance (e.g., overall communication and/orparticular communication related operations and functions, and/orcomponents used therefor) may need to be optimized, such as to meetcertain performance parameters, criteria, and/or conditions, and/or toaccount for possible conditions that may degrade performance. Forexample, reception operations (and/or components used therefor, such asthe receiver 170 and/or Rx processing path 180) may be need to beconfigured to support wide carrier frequency range (e.g., 5-43.5 GHz)and a wide bandwidth (e.g., 1.75-224 MHz) while still ensuring optimalperformance (e.g., high modulation error ratio (MER) at the IF output).Such performance criteria may necessitate, among other things, highlinearity requirements. However, the performance of the receiver may bedegraded in some situations, such as in a manner that may affect thelinearity characteristics of the receiver. For example, in someinstances certain unwanted signals (e.g., blockers) may limit theperformance of the receiver, causing nonlinearities under someconditions, as explained in more detail below.

Accordingly, in various implementations in accordance with the presentdisclosure, communication systems (or components thereof) may beimplemented to ensure optimal linearity while still meeting otherperformance requirement. This may be achieved, for example, byincorporating support for adaptive nonlinearity detection andestimation, and for nonlinearity cancellation based thereon, at thereceiver-side. Examples of such implementations are described in moredetail below.

While the receiver-side architecture shown in FIG. 1 and referencedhereafter (e.g., with respect to various implementations in accordancewith the present disclosure) may be a (low) IF based architecture, thedisclosure is not so limited. Thus, in some instances a zero-IF receivedarchitecture may implement and/or utilize various aspects of the presentdisclosure (e.g., implementations, techniques, etc.).

FIG. 2 illustrates an example analog front-end (AFE) in whichnonlinearity may occur during reception operations. Shown in FIG. 2 isanalog front-end AFE block 200, which may be used during receptionoperations.

The AFE block 200 may comprise suitable circuitry for use in receivingand processing signals. The AFE block 200 may comprise an amplificationcomponent 210, a mixing component 220, and a conversion component 230.The amplification component 210 may comprise suitable circuitry forperforming initial amplification on an input (e.g., received RF signal).The amplification component 210 may comprise, for example, a low-noiseamplifier (LNA) circuit 212.

The mixing component 220 may comprise suitable circuitry for mixing (andperforming related functions and/or operations) to the input (RF signal)after the initial amplification. The mixing component 220 may beoperable to, for example, generate the in-phase and quadraturecomponents (I/Q components) of the input signals. For example, themixing component 220 may comprise a pair of mixer circuits 222 ₁ and 222₂, a pair of filter circuits 224 ₁ and 224 ₂, and a pair ofvariable-gain amplifier (VGA) circuits 226 ₁ and 226 ₂. Further, themixing component 220 may comprise a voltage-controlled oscillator (VCO)circuit 228, which provides a reference mixing signal, and an adjustercircuit 229, which may be operable to apply an adjustment (e.g., 90°shift) to the output of the VCO circuit 228 (before being applied to oneof the mixer circuits 222 ₁ and 222 ₂), to facilitate the generation ofthe I/Q components. In some instances, the filter circuits 224 ₁ and 224₂ may be anti-aliasing filter (AAF) circuits, and as such the filteringperformed in the mixing component 220 may be anti-aliasing filtering.

The conversion component 230 may comprise suitable circuitry forapplying necessary conversions to the outputs of the mixing component220. For example, the conversion component 230 may comprise one or moreanalog-to-digital converter (ADC) circuits—e.g., ADC circuits 232 ₁ and232 ₂ in the implementation shown in FIG. 2, each being used to applyanalog-to-digital conversion to each of the I/Q components generated inthe mixing component 220.

As shown in FIG. 2, the AFE block 200 may exhibit nonlinearity behavior,which may be result in the system failing to meet linearity requirementsneeded to meet overall performance criteria. The nonlinearity behaviorof the AFE block 200 may be due to third-order intercept point (IP3)and/or second-order intercept point (IP2) characteristics of each of thevarious components of the system, which may result in intermodulation(IM) and/or harmonic distortion (HD) related nonlinearities at theoutputs. Examples IM/HD scenarios are described in more detail withrespect to FIGS. 3A and 3B. Nonetheless, while many of theimplementations described are directed to second-order and/or thirdorder nonlinearities (or effects thereof), the disclosure is not solimited. In this regard, a similar approach as described in the presentdisclosure may apply in substantially similar manner to other (e.g.,higher) order nonlinearities, such as (e.g., fourth-order interceptpoint (IP4), fifth-order intercept point (IP5), etc.).

FIGS. 3A and 3B illustrate example impacts of intermodulation (IM) andharmonic distortion (HD) during reception operations. Shown in FIGS. 3Aand 3B are frequency charts 300 and 350, respectively.

The frequency chart 300 illustrates an example scenario where 3rd orderproducts (e.g., 3rd order intermodulation (IM3), crossmodulation (XMOD),and baseband (BB) 3rd order harmonic distortion (HD3)) may affect adesired signal 301 in the processing path, such as during the mixingand/or conversion stages—e.g., in the mixing component 220 and/orconversion component 230. The desired signal 301 may be at frequencylocation IF (intermediate frequency), such as after shifting duringinitial processing in the RF receiver. The 3rd order products may thenaffect the desired signal 301 (that is, fall at frequency location IF)when the causing signals (e.g., transmit (Tx) leakage 303, blockers 305_(i), etc.) may be at particular frequency locations. For example, IM3may occur as a result of the combined effect of the Tx leakage 303 thatis at frequency location IF+DS, and a blocker 305 ₁, within the firstreceiver (Rx) diplexer, at frequency location IF+DS/2. In this regard,DS is the Duplex Spacing frequency, which is defined in a FDD system asthe fixed frequency separation at RF between the TX signal and the RXsignal. The Tx leakage 303 may result in such systems from the Tx(signal) leaking thru the diplexer on to the receiver path. The BB HD3may occur as a result of a second blocker 305 ₂ in a second receiver(Rx) diplexer, whereas the XMOD may occur as a result of another blocker305 ₃.

The frequency chart 350 illustrates an example scenario where 2nd orderproducts (e.g., 2nd order intermodulation (IM2) and 2nd order harmonicdistortion (HD2)) may occur while a receiver attempts to capture adesired signal 351 in the processing path, such as during the mixingand/or conversion stages—e.g., in the mixing component 220 and/orconversion component 230. The desired signal 351 may again be atfrequency location IF. The 2nd order products may then affect thedesired signal 351 (that is, fall at frequency location IF) when thecausing signals (e.g., transmit (Tx) leakage 353, blockers 355 _(i),etc.) may be at particular frequency locations. For example, IM2 mayoccur as a result of the combined effect of the Tx leakage 353 that isat frequency location IF+DS, and a blocker 355 ₁, within the firstreceiver (Rx) diplexer, at frequency location DS. The HD2 may occur as aresult of a blocker 355 ₂, within the second receiver (Rx) diplexer, atfrequency location IF/2, and/or a result of a blocker 355 ₃ within thesecond receiver (Rx) diplexer, at frequency location −IF/2.

As noted above, the 2nd order and/or 3rd order products may result innonlinearity behavior in the communication system during receptionoperations. Accordingly, in various implementations in accordance withthe present disclosure, communication systems (or components thereof)may be implemented and/or configured to remedy undesirablenonlinearities, particularly during reception operations. For example,communication systems may incorporate components that are designedand/or configured to support performing adaptive nonlinearity detectionand estimation, and applying nonlinearity cancellation based thereon.The nonlinearity detection may comprise assessing the presence ofnonlinearity. This may comprise, for example, determining if there aredistorting signals (e.g., blockers, Tx leakage, etc.) which may causenonlinearity related distortion, and if so, determine if the distortingsignals (individually or in combination) may actually causenonlinearity—e.g., whether these distorting signals may hitpre-determined IP2/IP3 locations, thus resulting in 2nd order and/or 3rdorder distortion (e.g., IM2, IM3, HD2, HD3, XMOD, etc.). Oncenonlinearity is detected, remedial measures may be taken to cancel thenonlinearities or effects thereof. This may entail estimating thenonlinearity (effects), such that the proper corrections may bedetermined (or estimated). The nonlinearity estimation and/or correctionthereof may be configured based on the required SNR (signal-to-noiseratio) rather than nonlinearity parameters (e.g., IP2/IP3 numbers).

In an example implementation, to optimize performance estimation ofnonlinearity (or necessary correction thereof) may be performed asnarrowband (NB) estimation—that is, based on narrowband signals (orchannels); whereas the correction may be performed as wideband (WB)correction—that is, the nonlinearity (NL) cancellation is applied towideband signals. Use of such combination of narrowband (NB) estimationand wideband (WB) correction may be optimal because the NB estimationmay be more power efficient (than WB estimation) and WB correction (NLcancellation) may be more robust (e.g., against TDD blockers andsweeping blockers).

In an example implementation, the nonlinearity estimation (and thedetermination of required nonlinearity corrections based thereon) maycomprise analyzing the whole spectrum, such as to obtain informationuseful for nonlinearity estimation and/or correction (e.g., to determinepresence and location of desired signals and/or particular blockers).Further, other means beyond what is specifically described herein may beused in detecting and/or estimating (and thus determining neededcorrections) nonlinearity, such as, for example, AM-AM and AM-PM look uptable models.

FIG. 4 illustrates example architecture for nonlinearity correction inreceiver analog front-ends, using narrowband (NB) nonlinearityestimation and wideband (WB) nonlinearity correction. Shown in FIG. 4 isprocessing block 400.

The processing block 400 may comprise suitable circuitry for performingnonlinearity estimation and correction during reception operations. Inparticular, the processing block 400 may be configured to performnarrowband (NB) estimation and wideband (WB) correction ofnonlinearities during reception operations. The processing block 400 maybe incorporated into a communication system to provide nonlinearitycorrections. For example, with reference to the front-end AFE block 200of FIG. 2, the processing block 400 may be implemented or addedfollowing conversion component 230, thus receiving as input the ADCsignal(s) outputted by the ADC circuit(s) 232 _(i). The processing block400 (or components thereof) may be implemented as a new dedicatedelement—e.g., new dedicated circuitry added to the communication system.Alternatively, the processing block 400, or at least some components(e.g., circuits) thereof, may correspond to existing component(s) in thehost communication system, which may simply be configured to perform thefunctions associated with the processing block 400 as described in thisdisclosure.

The processing block 400 may comprise an ADC/IQ calibration circuit 410,a wideband (WB) anti-aliasing filtering (AAF) compensation circuit 420,a wideband (WB) nonlinearity cancellation circuit 430, a channelizercircuit 440, a narrowband (NB) estimation circuit 450, a received signalstrength indicator (RSSI) circuit 460, and a controller circuit 470.

The ADC/IQ calibration circuit 410 may be operable to calibrate inputADC signal(s), and/or input I/Q components (e.g., corresponding to theADC signal(s)).

The WB AAF compensation circuit 420 may be operable to performanti-aliasing filtering compensation to an input signal (correspondingto the received signal). In this regard, the anti-aliasing filteringperformed in the receiver (e.g., via the filter circuits 224 ₁ and 224 ₂of the AFE block 200 FIG. 2, when implemented as anti-aliasing filter(AAF) circuits) may also include blocker filtering. Thus, the blockersmay have to be reconstructed in the digital domain, which is done by theWB AAF compensation circuit 420, in order to cancel the nonlinearityeffects added in the AFE before the AAF filter. The signal(s) handled inthe WB AAF compensation circuit 420 is a (or are) wideband signal(s).The WB AAF compensation circuit 420 may comprise, for example, again-stage circuit 422, which may be operable to apply a particular gain(e.g., set or provided by the controller circuit 470), and acompensation-stage circuit 424, which may be operable to apply aparticular compensation associated with anti-aliasing filtering—e.g.,performed in the processing path, prior to the processing block 400.

The WB nonlinearity cancellation circuit 430 may be operable to performwideband nonlinearity cancellation on the input signal, after havingapplied anti-aliasing filtering compensation thereto via the WB AAFcompensation circuit 420. The signal(s) processed in the WB nonlinearitycancellation circuit 430 is a (or are) wideband signal(s). The WBnonlinearity cancellation circuit 430 may be configured to correct onlysecond-order intermodulation (IM2) and third-order intermodulation(IM3), but not for higher order (or other types of) nonlinearity. Forexample, as shown in FIG. 4 the WB nonlinearity cancellation circuit 430may comprise an IM2 cancellation circuit 432, an IM3 cancellationcircuit 434, and an adder circuit 436. Thus, the WB nonlinearitycancellation circuit 430 may only include IM2 and IM3 cancellationcomponents. The disclosure is not so limited, however, and WBnonlinearity cancellation performed by circuit 430 may be implemented toapply to other types and/or higher orders of nonlinearity.

The IM2 cancellation circuit 432 is operable to apply IM2 cancellation,such as to the input signal. Similarly, the IM3 cancellation circuit 434is operable to apply IM3 (e.g., including RF IM3 and BB IM3)cancellation, such as to the input signal. The IM2 cancellation circuit432 and/or the IM3 cancellation circuit 434 may be operable to apply therespective cancellation performed thereby based on control signals(e.g., comprising control parameters) from the controller circuit 470.Outputs of the IM2 cancellation circuit 432 and the IM3 cancellationcircuit 434, as well as a copy of the signal inputted into the WBnonlinearity cancellation circuit 430 (from the WB AAF compensationcircuit 420) are then combined via the adder 436.

The channelizer circuit 440 may be operable to channelize the inputsignal, after having applied anti-aliasing filtering compensation andwideband nonlinearity cancellation thereto, via the WB AAF compensationcircuit 420 and the WB nonlinearity cancellation circuit 430,respectively. In this regard, the channelizer 440 may be operable toextract one or more narrowband (NB) channels from the original widebandsignal.

The NB estimation circuit 450 may be operable to generate, such as basedon channelization information obtained from the channelizer circuit 440,information relating to possible second-order and/or third-orderproducts and their locations within the wideband signal being receivedand processed. That information may be provided to the controllercircuit 470, which may use it—e.g., in determining and/or generatingnonlinearity related control information.

The RSSI circuit 460 may be operable to generate, such as based on asignal received from the WB AAF compensation circuit 420 (output aftercompensation applied by the compensation-stage circuit 424), RSSIrelated information (and/or other types of power related measurementpertaining to the input signal). That information may be provided to thecontroller circuit 470, which may use it—e.g., in determining and/orgenerating control information used in the processing block 400. Forexample, the RSSI measurements provided by the RSSI circuit 460 may beused in controlling and/or configuring the AAF compensation applied bythe of the AAF compensation circuit 420, such as by setting and/oradjusting the gain applied at the gain-stage circuit 422 and/or thecompensation applied at the compensation-stage circuit 424. The RSSImeasurements provided by the RSSI circuit 460 may also be used incontrolling and/or configuring the nonlinearity correction (e.g.,cancellation) based on target signal-to-noise ratio (SNR), which may beassessed or determined based on RSSI measurements, and/or in settingand/or adjusting the gain applied at the gain-stage circuit 422 in theAAF compensation circuit 420.

The controller circuit 470 may be operable to control overall operationsof the processing block 400. For example, the controller circuit 470 mayreceive information from various components of the processing block 400,may process that information, and may generate control information(e.g., arrangement, configuration, and/or operational related data) forvarious components in the processing block 400. The controller circuit470 may be, for example, a central processing unit (CPU) or other typeof processor (general-purpose or special-purpose). With respect tononlinearity correction operations, the controller circuit 470 mayreceive nonlinearity (or signal) related information (e.g., RSSImeasurements from the RSSI circuit 460, 2nd/3rd order related productinformation from the NB estimation circuit 450, etc.), may process thatinformation, and generate control information for various components inthe processing block 400—e.g., the gain applied at the gain-stagecircuit 422, the compensation applied at the compensation-stage circuit424, the cancellation applied by the IM2 cancellation circuit 432 and/orthe IM3 cancellation circuit 434, etc.

In operation, the processing block 400 may be operable to apply wideband(WB) correction and narrowband (NB) estimation to an input signal. Thesignal may be an intermediate signal in a reception processing path. Forexample, the input signal to the processing block 400 may be an ADCsignal (e.g., output(s) of the ADC circuit(s) 234 _(i) of FIG. 2). TheWB nonlinearity cancellation circuit 430 may be adaptively configured toimplement a particular nonlinearity correction model. At least some ofthe parameters used in the correction model may be determineddynamically and continually (e.g., based on RSSI measurement,nonlinearity estimation, etc.), such as by the controller circuit 470,which may then provide them to the WB nonlinearity cancellation circuit430.

In an example implementation, the nonlinearity correction model appliedduring WB cancellation (e.g., in the WB nonlinearity cancellationcircuit 430) may be configured to correct only IM2 and IM3 (but not forhigher order nonlinearity). Nonetheless, it should be understood thatthat the disclosure is not so limited, and that other (higher) ordernonlinearities may also be handled (estimated and/or corrected) in asubstantially similar manner (with the particular model being used beingadjusted accordingly). Thus, the WB nonlinearity cancellation circuit430 may only include IM2 and IM3 cancellation components (the IM2cancellation circuit 432 and the IM3 cancellation circuit 434). Anexample correction model is now described. The incoming signal may beexpressed as:

S(t)=S _(I)(t)+jS _(Q)(t)  (1)

The radio frequency (RF) IM3 corrections may be performed as follows:

coef_rf_im3×S(t)×∥S(t)∥²  (2)

The baseband (BB) IM3 corrections may be performed (at I and Q paths,respectively) as:

coef_bb_im3×S_(I)(t)³  (3)

coef_bb_im3×S_(I)(t)³  (4)

The baseband (BB) IM2 corrections may be performed (to the real andimaginary paths, respectively) as:

coef_bb_im2_r×S_(I)(t)²  (5)

coef_bb_im2_i×S_(Q)(t)²  (6)

The controller circuit 470 may determine the different coefficients(coef_rf_im3, coef_bb_im3, coef_bb_im2_r, and coef_bb_im2_i) based on,for example, the feedback received from the NB estimation circuit 450and/or the control input from the RSSI circuit 460.

Nonetheless, while the processing block 400 is shown as only providingIM2/IM3 detection and cancellation, in some implementations, theprocessing block 400 may be configured to also detect and correct othertypes of nonlinearity products—e.g., 2nd order and/or 3rd order harmonicdistortion (HD2/HD3), particularly where doing so may not require toomuch additional processing. For example, the processing block 400 may beoperable to perform HD2/HD3 aliasing check (and correction basedthereon). In this regard, it may be determined whether the HD2/HD3 ofthe blocker(s) (e.g., from the cancellation circuit) may fall onparticular locations, such as IF±Fs (Fs=sampling frequency), and causealiasing. In instances where the frequency of such blocker is less than(or equal) desired frequency, there may be no impact (thus no action maybe needed). Where the blocker frequency is greater than the desiredfrequency, however, HD2 correction and HD3 correction may be removed.Further, in some instances, while removing HD3 correction, it may beadded back to the crossmodulation (XMOD) correction term.

FIG. 5 illustrates example architecture for narrowband (NB) nonlinearityestimation and wideband (WB) nonlinearity correction. Shown in FIG. 5 isprocessing block 500.

The processing block 500 may be similar to the processing block 400 ofFIG. 4, for example. In this regard, the processing block 500 maycomprise suitable circuitry for performing nonlinearity estimation andcorrection during reception operations. In particular, the processingblock 500 may be operable to perform wideband (WB) nonlinearitycancellation and narrowband (NB) nonlinearity estimation. In the exampleimplementation, the processing block 500 (or portion thereof) as shownin FIG. 5 may comprise an ADC/IQ calibration circuit 510, a wideband(WB) anti-aliasing filter (AAF) compensation circuit 520, a wideband(WB) nonlinearity cancellation circuit 530, a desired signal (DS)channelizer circuit 540, an estimated signal (ES) channelizer circuit550, a blocker channelizer circuit 560, a narrowband (NB) referencegenerator circuit 570, a coefficient estimation circuit 580, and a (CFS)filter circuit 590.

Each of the ADC/IQ calibration circuit 510, the AAF compensation circuit520, and the WB nonlinearity cancellation circuit 530 may be similar to,and may operate in substantially similar manner as the corresponding(and similarly named) element in the processing block 400 of FIG. 4—thatis, the ADC/IQ calibration circuit 410, the WB AAF compensation circuit420, and the WB nonlinearity cancellation circuit 430. Further, as notedwith respect to the WB nonlinearity cancellation circuit 430 inparticular (and the processing block 400 as a whole), while theprocessing block 500 and the nonlinearity estimation and correctionrelated components and/or functions thereof may be described as beingdirected to correctly only second- and third-order nonlinearities (e.g.,IM2 and IM3) but not for higher order nonlinearity), this is only anexample implementation. Thus, in other implementations other (e.g.,higher) order nonlinearities may also be handled (estimated and/orcorrected) in substantially similar manner (with the pertinentcomponents and/or functions being adjusted accordingly).

The DS channelizer circuit 540, the ES channelizer circuit 550, and theblocker channelizer circuit 560 may (individually and/or collectively)be operable to provide channelization function substantially in similarmanner as the channelizer circuit 440 does in the processing block 400of FIG. 4. In this regard, each of the DS channelizer circuit 540, theES channelizer circuit 550, and the blocker channelizer circuit 560 maybe operable to channelize an input signal, and/or to generatechannelization information related thereto. For example, as shown inFIG. 5, each of these elements may receive a copy of the same inputsignal, which may correspond to the output of the WB cancellationcircuit 530, and may apply channelization function thereto. Each of theDS channelizer circuit 540, the ES channelizer circuit 550, and theblocker channelizer circuit 560, however, may be configured to performthe channelization function based on different criteria. For example,the DS channelizer circuit 540 may be configured to extract and/orgenerate “desired” signal channels, and/or to generate channelizationinformation relating thereto. The ES channelizer circuit 550 may beconfigured to extract and/or generate estimation signal channels, and/orto generate channelization information relating thereto. The blockerchannelizer circuit 560 may be configured to extract and/or generatechannelization information relating to blockers.

The NB reference generator circuit 570 may be operable to generatereference nonlinearity information relating to and/or associated withthe blockers.

The coefficient estimation circuit 580 may be operable to generatecontrol (estimation-related) feedback, which may be used (e.g., via acontroller, such as control circuit 470 of FIG. 4) to generateinformation relating to control of nonlinearity cancellation. Theinformation may comprise, for example, coefficients applied or usedduring wideband anti-aliasing filtering compensation (e.g., within theWB AAF compensation circuit 520) and/or wideband cancellation (e.g.,within the WB cancellation circuit 530).

The CFS filter circuit 590 may be operable to extract a narrow bandportion of a signal that can be used for the purpose of estimation ofthe nonlinearity capture in the frequency band.

FIG. 6 illustrates an example narrowband (NB) reference generator andcoefficient estimator used for narrowband (NB) nonlinearity estimation.Shown in FIG. 6 is a portion of the processing block 500 of FIG. 5,particularly the ES channelizer circuit 550, the blocker channelizercircuit 560, the NB reference generator circuit 570, the coefficientestimation circuit 580, and the CFS filter circuit 590.

In this regard, illustrated in FIG. 6 are example implementations of NBreference generator circuit 570 and the coefficient estimation circuit580, for providing second-order and third-order nonlinearity estimationand corrections (in the processing block 500). Nonetheless, it should beunderstood that while this specific implementation estimates andcorrects only for second- and third-order nonlinearities, systems andmethods implemented in accordance with the present disclosure may beextended to and/or applied in substantially similar manner in estimationand cancellation of other (higher) order nonlinearities.

As shown in FIG. 6, the NB reference generator circuit 570 may comprisean N-to-3 multiplexer (Mux) 610, plurality of conjugate function blocks620 ₁-620 ₃, a plurality of 2-to-1 multiplexers (Mux) 630 ₁-630 ₃, aplurality of delay blocks 640 ₁-640 ₄, a plurality of multipliers 650₁-650 ₂, and DC notch block 660. These elements may be arranged withinthe NB reference generator circuit 570, for example, in the mannerillustrated in the example implementation depicts in FIG. 6. Thecoefficient estimation circuit 580 may comprise an estimation delayblock 670 and an estimation engine block 680. These elements may bearranged within the coefficient estimation circuit 580, for example, inthe manner illustrated in the example implementation depicts in FIG. 6.

Each of the plurality of delay blocks 640 ₁-640 ₄ may be configured toapply particular delays that may be needed to account for and/oraccommodate processing or functions performed in NB reference generatorcircuit 570. For example, the delay blocks 640 ₁-640 ₃ may apply oneclock cycle delay whereas the delay block 640 ₄ may introduce two clockcycles delay. The DC notch block 660 may be configured to remove (e.g.,filter out) DC component(s). In this regard, the DC notch block 660 maybe implemented as a filter circuit.

The estimation delay block 670 may be configured to apply a particulardelay. In this regard, the delay applied by the estimation delay block670 may be set or adjusted adaptively and/or dynamically. The estimationdelay block 670 may introduce delay in the estimation path to accountfor processing in other paths—e.g., with respect to the desired signalchannelization and/or the estimation signal channelization. Accordingly,the delay introduced by the estimation delay block 670 may ensure thatthe estimation function may be lines up with the desired signal(channels).

The estimation engine block 680 may be configured to generate estimationrelated data, such as nonlinearity estimation-based coefficients (ordata that may be used in generating such coefficients such as by aseparate controller element—e.g., the controller circuit 470 of FIG. 4).The estimation function performed via the estimation engine block 680(e.g., to estimate required coefficients for correction/cancellationoperations), may be implemented, for example, as least-mean-square (LMS)based function, blind-source separation (BSS) based function, etc.

In an example implementation, various measures may be taken during thechannelization and/or estimation operations, to ensure that theseoperations, and subsequent operations performed based thereon (e.g.,nonlinearity correction) are lined up correctly with the actual (e.g.,desired) signals being handled. For example, two stages ofsynchronization may be performed, including a first-stagesynchronization that is performed by the channelizer elements (e.g., ESchannelizer circuit 550 and the blocker channelizer circuit 560), andsecond-stage synchronization which may be applied during estimation step(e.g., with the delay applied by the estimation delay block 670 beingused to ensure that).

FIG. 7 illustrates example anti-aliasing filtering (AAF) compensationcircuit for use in nonlinearity correction in receiver analogfront-ends. Shown in FIG. 7 is an anti-aliasing filtering (AAF)compensation circuit 700.

The AAF compensation circuit 700 may be operable to apply compensationassociated with anti-aliasing filtering. For example, the AAFcompensation circuit 700 may be to support wideband (WB) anti-aliasingfiltering compensation. In this regard, the AAF compensation circuit 700may represent an example implementation of the WB AAF compensationcircuit 420 of FIG. 4 (or the WB AAF compensation circuit 520 of FIG.5).

As shown in FIG. 7, the AAF compensation circuit 700 may comprise aplurality of delay blocks 710 ₁-710 ₄, a plurality of adders 720 ₁-720₈, a plurality of multipliers 730 ₁-730 ₅, and a post-processing(applying post-processing functions, such as round-and-saturation (rns)function) block 740. These elements may be arranged, for example, in themanner illustrated in the example implementation depicted in FIG. 7.

Each of the plurality of delay blocks 710 ₁-710 ₄ may be configured toapply particular delays that may be needed to account for and/oraccommodate processing or functions performed in the AAF compensationcircuit 700. For example, each of the delay blocks 710 ₁-710 ₄ may applyone clock cycle delay.

The compensation performed by the AAF compensation circuit 700 may beadjusted, adaptively, by adjusting a plurality of compensationcoefficients (coef0-coef4) which may be applied in the AAF compensationcircuit 700—being input into the multipliers 720 ₁-720 ₅, as shown inFIG. 7.

The compensation coefficients coef0-coef4 may be set and/or adjusted bya controller element (e.g., the controller circuit 470 in FIG. 4), whichmay calculate and/or determine these compensation coefficients, such asbased on preset data and/or dynamically obtained control data. Forexample, the compensation coefficients coef0-coef4 may be determined oradjusted, at least in part, based on signal related measurements (e.g.,RSSI measurements, such as those provided by the RSSI circuit 460 inFIG. 4).

FIG. 8 illustrates example nonlinearity cancellation circuit for use innonlinearity correction in receiver analog front-ends. Shown in FIG. 8is a nonlinearity (NL) cancellation circuit 800.

The NL cancellation circuit 800 may be operable to apply compensationassociated with anti-aliasing filtering. For example, the NLcancellation circuit 800 may be operable to support wideband (WB)nonlinearity cancellation. In this regard, the NL cancellation circuit800 may represent an example implementation of the WB cancellationcircuit 430 of FIG. 4 (or the WB cancellation circuit 530 of FIG. 5).

As shown in FIG. 8, the NL cancellation circuit 800 may comprise aplurality of delay blocks 810 ₁-810 ₆, a plurality of adders 820 ₁-820₄, a plurality of multipliers 830 ₁-830 ₁₀, a plurality ofpost-processing (e.g., round-and-saturation (rns) function) blocks 840₁-840 ₂, and plurality of square function blocks 850 ₁-850 ₂. Theseelements can be arranged in the manner illustrated in the exampleimplementation depicts in FIG. 8.

Each of the plurality of delay blocks 810 ₁-810 ₆ may be configured toapply particular delays that may be needed to account for and/oraccommodate processing or functions performed in the NL cancellationcircuit 800. For example, each of the delay blocks 810 ₁-810 ₆ may applyone clock cycle delay.

The nonlinearity cancellation performed by the NL cancellation circuit800 may be adjusted, adaptively, by adjusting a plurality of NLcancellation coefficients (e.g., which may be applied in the AAF NLcancellation circuit 800—being input into some of the multipliers 830₁-830 ₁₀, as shown in FIG. 8.

The NL cancellation coefficients may be set and/or adjusted by acontroller element (e.g., the controller circuit 470 in FIG. 4), whichmay calculate and/or determine these NL cancellation coefficients, suchas based on preset data and/or dynamically obtained control data. Forexample, the NL cancellation coefficients may be determined or adjusted,at least in part, based on nonlinearity estimation (e.g., narrowband(NB) estimation, such as those provided by the NL estimator circuit 450in FIG. 4; or by coefficient estimator circuit 580 in FIG. 5).

In the example implementation shown in FIG. 8, NL cancellationcoefficients may be configured for use in cancelling 2nd order and 3rdorder intermodulation (IM2 and IM3). In this regard, the NL cancellationcoefficients may be set based on the correction model implemented in thesystem. For example, the NL cancellation coefficients as shown in FIG. 8may be determined, based on the coefficients associated with thecorrection model described with respect to FIG. 4, as follows:

coef_im3_1_r=coef_rf_im3+coef_bb_im3  (7)

coef_im3_1_i=coef_rf_im3+coef_bb_im3  (8)

coef_im3_2_r=coef_rf_im3  (9)

coef_im3_2_i=coef_rf_im3  (10)

coef_im2_r=coef_bb_im2_r  (11)

coef_im2_i=coef_bb_im2_r  (12)

FIG. 9 illustrates a flowchart of an example process for nonlinearitydetection and correction during communications. Shown in FIG. 9 is flowchart 900, comprising a plurality of example steps (represented asblocks 902-914).

In start step 902, a signal (e.g., RF signal) may be received (e.g., viaa RF transceiver), and a corresponding IF signal may be generated.

In step 904, initial processing (e.g., LNA, Mixing, AAF, ADC) may beapplied to the received signal.

In step 906, it may be determined whether there any blockers (and/or Txleakage). If so, the process may proceed to step 908; otherwise theprocess may jump to step 914.

In step 908, it may be determined whether any of the blockers may hitthe 2nd order and/or 3rd order (IP2/IP3) locations. If so, the processmay proceed to step 910; otherwise the process may jump to step 914.

In step 910, nonlinearity caused by blockers may be estimated (e.g.,using narrowband (NB) estimation, as described with above.

In step 912, nonlinearity correction may be applied (e.g., usingwideband (NB) cancellation, as described with above.

In step 914, the processing of the input signal may continue, toobtain/generate desired signal (channels).

Other embodiments of the invention may provide a non-transitory computerreadable medium and/or storage medium, and/or a non-transitory machinereadable medium and/or storage medium, having stored thereon, a machinecode and/or a computer program having at least one code sectionexecutable by a machine and/or a computer, thereby causing the machineand/or computer to perform the processes as described herein.

Accordingly, various embodiments in accordance with the presentinvention may be realized in hardware, software, or a combination ofhardware and software. The present invention may be realized in acentralized fashion in at least one computing system, or in adistributed fashion where different elements are spread across severalinterconnected computing systems. Any kind of computing system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware and software may be ageneral-purpose computing system with a program or other code that, whenbeing loaded and executed, controls the computing system such that itcarries out the methods described herein. Another typical implementationmay comprise an application specific integrated circuit or chip.

Various embodiments in accordance with the present invention may also beembedded in a computer program product, which comprises all the featuresenabling the implementation of the methods described herein, and whichwhen loaded in a computer system is able to carry out these methods.Computer program in the present context means any expression, in anylanguage, code or notation, of a set of instructions intended to cause asystem having an information processing capability to perform aparticular function either directly or after either or both of thefollowing: a) conversion to another language, code or notation; b)reproduction in a different material form.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

What is claimed is:
 1. A method for performing narrowband (NB)estimation, the method comprising: generating estimation channelizationinformation relating to received RF signals; generating referencenonlinearity information relating to one or more other signals, whereinthe one or more other signals cause or contribute to nonlinearity thataffects processing of the received RF signals; and generating, based onthe estimation channelization information relating to the received RFsignals and the reference nonlinearity information relating to the oneor more other signals, control data for configuring nonlinearitycancellation functions.
 2. The method of claim 1, comprising:channelizing the received RF signals; and generating the estimationchannelization information based on the channelization of the receivedRF signals.
 3. The method of claim 2, comprising: extracting during thechannelization of the received RF signals, one or more narrowband (NB)channels; and generating the estimation channelization information basedon the extracted one or more narrowband (NB) channels.
 4. The method ofclaim 1, comprising: channelizing the one or more other signals; andgenerating the reference nonlinearity information based on thechannelization of the one or more other signals.
 5. The method of claim4, comprising: obtaining a plurality of channels based on thechannelization of the one or more other signals; and generating thereference nonlinearity information based on processing of the pluralityof channels.
 6. The method of claim 5, comprising selecting a subset ofchannels, and processing only each of the subset of channels.
 7. Themethod of claim 6, comprising applying a conjugate function basedadjustment to one or more of the subset of channels.
 8. The method ofclaim 6, comprising applying a DC notch based adjustment to at least oneor the subset of channels, the DC notch based adjustment comprisingremoving DC components.
 9. The method of claim 6, comprising applyingone or more delays to synchronize processing of each of the subset ofchannels.
 10. The method of claim 1, comprising applying a delay tosynchronize the generating of the estimation channelization informationrelating to the received RF signals and the generating of the referencenonlinearity information relating to the one or more other signals. 11.A system comprising: one or more circuits for performing narrowband (NB)estimation, the one or more circuits being configured to: generateestimation channelization information relating to received RF signals;generate reference nonlinearity information relating to one or moreother signals, wherein the one or more other signals cause or contributeto nonlinearity that affects processing of the received RF signals; andgenerate, based on the estimation channelization information relating tothe received RF signals and the reference nonlinearity informationrelating to the one or more other signals, control data for configuringnonlinearity cancellation functions.
 12. The system of claim 11, whereinthe one or more circuits are configured to: channelize the received RFsignals; and generate the estimation channelization information based onthe channelization of the received RF signals.
 13. The system of claim12, wherein the one or more circuits are configured to: extract duringthe channelization of the received RF signals, one or more narrowband(NB) channels; and generate the estimation channelization informationbased on the extracted one or more narrowband (NB) channels.
 14. Thesystem of claim 11, wherein the one or more circuits are configured to:channelize the one or more other signals; and generate the referencenonlinearity information based on the channelization of the one or moreother signals.
 15. The system of claim 14, wherein the one or morecircuits are configured to: obtain a plurality of channels based on thechannelization of the one or more other signals; and generate thereference nonlinearity information based on processing of the pluralityof channels.
 16. The system of claim 15, wherein the one or morecircuits are configured to select a subset of channels, and processingonly each of the subset of channels.
 17. The system of claim 16, whereinthe one or more circuits are configured to apply a conjugate functionbased adjustment to one or more of the subset of channels.
 18. Thesystem of claim 16, wherein the one or more circuits are configured toapply a DC notch based adjustment to at least one or the subset ofchannels, the DC notch based adjustment comprising removing DCcomponents.
 19. The system of claim 16, wherein the one or more circuitsare configured to apply one or more delays to synchronize processing ofeach of the subset of channels.
 20. The system of claim 11, wherein theone or more circuits are configured to apply a delay to synchronize thegenerating of the estimation channelization information relating to thereceived RF signals and the generating of the reference nonlinearityinformation relating to the one or more other signals.